1. Field of the Invention
The present invention relates to semiconductor technology, and specifically to MOS technology. More particularly, the present invention relates to radiation hardened MOS transistors and to methods for fabricating such transistors.
2. Description of Related Art
The present invention is intended to solve the problem of transistor off-state leakage in n-channel MOS (NMOS) high-voltage (HV) transistors due to ionizing radiation. Ionizing radiation over time deposits positive charge in the insulating materials surrounding the transistor, causing NMOS devices to exhibit large parasitic drain-to-source leakages by creation of an inverted channel along the transistor sidewalls. These large leakage currents limit the usable lifetime of NMOS transistors in radiation environments. Due to the lower body doping of HV transistors, these devices are especially vulnerable to this failure mechanism.
Total Ionizing Dose (TID) is a long-term degradation of electronics due to the cumulative energy deposited in a material. Typical effects include parametric failures, or degradations in device parameters such as increased leakage current, threshold voltage shifts, or functional failures. Major sources of TID exposure in the space environment include trapped electrons, trapped protons, and solar protons, as well as trapped charge in dielectrics caused by X-Rays and Gamma Rays and high-energy ions.
There are several transistor degradation modes caused as a result of ionization dose. One is a shift in threshold voltage Vt. The Vt of NMOS devices shifts in a negative direction and tends to turn on due to hole trapping in the gate oxide. Another is sidewall leakage.
The Vt of parasitic isolation sidewall transistors also shifts in a negative direction. For NMOS transistors, as Vt becomes more negative, sidewall leakage increases exponentially as the parasitic transistor starts to turn on at a lower threshold voltage. This is the primary lifetime limitation for standard medium voltage (MV) and high-voltage (HV) NMOS devices. Shallow-trench isolation (STI) accumulates positive charge during irradiation. The positive charge turns on parasitic sidewall transistors at the STI edges, forming an uncontrolled conducting path from drain to source.
FIGS. 1A through 1C illustrate the effects of TID on a typical linear NMOS STI isolated transistor. FIG. 1A is an isometric view of the structure, FIG. 1B is a cross-sectional view of the left-most portion of the structure taken through the drain, and FIG. 1C is a side view of the edge of the structure at the inner boundary of the STI isolation trench. Positive charge built up in the STI oxide (shown as multiple “+” signs in FIGS. 1A and 1B) lowers the threshold of the transistor, causing leakage current to flow from the drain to source along the edge of the structure through a parasitic transistor that exists at the gate edge proximate to the STI boundary, as shown by arrow 10 in FIGS. 1A and 1C.
Existing prior art layout solutions to this problem include transistors formed using annular gate geometries in which there are no isolation sidewalls connecting the drain and source nodes, because the gate completely encircles the drain of the transistor.
FIGS. 2A and 2B are top and cross-sectional views of an annular-gate transistor and illustrate an example layout of an existing annular-gate solution to the ionizing radiation problem for fabricating HV NMOS devices. The annular-gate transistor is fabricated within a boundary defined by an STI structure comprising a shallow trench filled with an insulating material, such as a deposited silicon dioxide. An annular polysilicon gate is formed and defined in the center of the transistor region defined by the STI structure. An annular source region and a square-shaped drain region are then implanted by a self-aligned-gate process using the annular gate as an implant mask, as is known in the art. The source comprises the region outside of the gate abutting the inner perimeter of the STI structure and the drain is formed through an aperture in the center of the gate.
As may be seen from an examination of FIGS. 2A and 2B, there is no drain edge at the inner STI periphery, since the annular source completely occupies the edge of the transistor structure. While this prevents the existence of a parasitic transistor at the gate edge at the STI region, since there is no gate edge at this location in the transistor, this solution to the problem is not entirely satisfactory.
In particular, it is difficult to scale width and length for transistor design in such structures. For example, SPICE models cannot easily be used to determine effective widths and lengths of such devices. Curved and circular structures are not provided for in conventional simulation software to model transistors. In addition, as geometries shrink, the right-angle edges of the structures in the annular gate transistor become disallowed in design rules, creating a lower limit on the size of such transistors. For example, below 65 nm, design rules prohibit 90° or even 45° angles on polysilicon over diffusion.
Another prior art solution to the problem when using lateral transistors with STI isolation has been to add an additional p-type implant to the diffusion sidewall. This implant is performed after trench etch and before trench fill. This solution delays the onset of parasitic leakage, but does not eliminate it. In addition, the additional sidewall implant degrades junction breakdown, which is problematic in HV transistors.
Another problem encountered in HV NMOS transistors is single-event transients and single-event latchups, caused by a heavy ion striking the drain region of the device while biased. Recovery from the strike is limited by the impedance to the body tap. This determines both the rate at which the (primary) injected charge can be collected, as well as how much transient forward bias develops at the junction, injecting additional (secondary) charge.
Existing solutions to the problem of HV NMOS single-event transients and single-event latchups involve the addition of additional well-tap diffusions to minimize the number of squares between a transistor active diffusion and tap diffusion. However these also increase the die area.